Power Amplifier

From specifications. A 10 mW RF power should be delivered to a 50 Ohm

DC analysis

Pout = I^2RL → I = 20 mA. To achieve biasing in class AB, the biasing current should be something in between, let's say 7.5 mA. in Fig. 1 we swept the width up to 30 m of the device to get the required current.

Fig. 1

Shown in Fig. 2, we could see that the transistor is in class AB PA and the drain-bulk breakdown is  Vdb = 1.6 V as shown in Fig. 3
The DC-power consumption:
Pdc = IdVdd = 7.5 mW = 8.7 dBm; for Vdd 1 V

Fig.2 {gm with respect to gate voltage (Blue curve) and drain current with respect to gate voltage.}


Fig.3 {The  drain-bulk breakdown at 0.4~V bias gate.}

Transient analysis

Fig. 4 {Input voltage swing (Average = 0.4 V), Drain current swing (Average = 8.5 mA)}

Cascode Topology
For the cascode topology, the output voltage swing is distributed across two transistors.

  Fig. 5 {Schematic amplifier design.}

  Fig. 6 {Max Available gain~(MAG)and Stability factor~(K_f) with respect at 6~fF neutralization capacitor.}

The effect of neutralization capacitor is not that significant. The amplifier is stable over a wide frequency range. From Fig.6 at frequency of 60~GHz, the MAG=20dB while the k_f=4.4
To design the input matching network, first we plot the input impedance seen into the amplifier Z_in~=~27.6-j144.37 Ohm. Fig.7 shows the real and imaginary parts of Z_in.

Fig. 7 {Real and Imaginary parts of Z_in.}

An LC matching network is used to perform the conjugate matching from the source to the input of the amplifier. Fig.8 shows a wide matching S-parameters

Fig. 8 {Input matching network S-parameters result.}

Load-pull simulations at output and the subsequent

For Load-pull simulation, we need a fixed input power level at which we calculate the optimal load. We can achieve the load-pull simulation in two different ways: increase the output saturated power, or increase the 1-dB compression point. Fig.9 shows the results of the power contours at input power of 10dBm, the optimal load seen by the PA is Z_L,opt=37.42+j82.68 Ohm. The output matching network is designed accordingly.

Fig. 9 {Power contours from load-pull simulations.}

Fig.10  shows the large signal PA's parameters after we matched to the load. The maximum achievable power (Saturated) is P_sat=8.9 dBm for P_in=dBm. Another load-pull simulation is achieved ( at P_in=2dBm) in order to boost the output saturated power.

Fig.10 {Large signal output parameters}

Fig.11 shows the large signal PA's parameters. The maximum achievable power (Saturated) is P_sat=11 dBm for P_in=5 dBm.

Fig. 11 {PA's large signal parameters, P_out=10.6~dBm and PAE=32.5 at P_in=2dBm

From Fig.11, the 1-dB compression point is about 4~dBm, which can be improved further.

         Final Schematic For class AB Cascode topology PA



Cross coupled LC oscillator with MOS capacitors to implement variable frequency tuning range. A differential amplifier is added as a second stage to act as a buffer with the aim to convert the sine wave generated by the oscillator to a square wave. The square wave is needed in the mixer.

Circuit topology:


Values of the RLC tank are follows: 1kOhm, 140pH, 20fF.

All the transistors have a width of 1.5um.

All the transistors except for the MOS capacitors have a length of 50nm. The MOS capacitors have a length of 1um.

Bias voltages of the tail transistors are 515mV for the oscillator and 520mV for the buffer.

The resistors used in the buffer have a value of 600Ohm.

The control voltage can range from 0V to 1V

Results of different transient anlyses:

Oscillation frequency of 60.01GHz with V_control =0.61V:


Oscillation frequency of 51.73GHz with V_control =0V:


Oscillation frequency of 69.72GHz with V_control =1V:







The circuit is a double balanced gilbert up-converter mixer.

Including a current source, made from a transistor. A resistor added in parallel to the transisor and LCR tank to reduce the current trough the latter, which will decrease the voltage drop across the LCR tank.


The oscillator input is a 60 GHz square wave input with goes from 680mV to 1.02mV.  This is the same as the output from our oscillator design. The input IF signal is a differential input with a sine wave with a dc voltage of 800mV and an amplitude of 140mV. The voltage source VDD is at 1V.

The values of the LCR (L, C, R2) tank are 100uH, 0F and 10k Ohm. In the original design a capacitor was used with extremely low values, which are not usually accesible. Changing the value of the capacitor to 0F, or thus an open did not change the output much.

The value of resitor R is 100k Ohm. The length of all transistors are 50 nm and the width of transistor of the current source is 90nm and all other transistors is 100nm.


Frequency divider of the synthesizer:

The circuit is a CML D-flipflop divide by 2 frequency divider.

The clk frequency is 60GHz. The resonance frequency of the divider is 31.8GHz according to calculations based on the RLC tank.

The used values in the RLC tank are: C=5fF, L=5nH, R=50K Ohm. The quality factor is 50 which gives a bandwidth of approximately 636 MHz.

All transistors used are the NMOS_VTL with width 90 nm and length 50nm.

The following image is the circuit created in Cadence:


Based on this circuit simlations in ADE L are executed. Visible in the following image is the clock signal and the 4 outputs of the divider. It can be noticed that the frequency of the outputs is half the clock frequency.


The output frequency of all outputs is also visible in the FFT simulation:


The highest peak visible in the FFT is at 30.6GHz. (almost half of 60GHz.)

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