On-Off-Keying (OOK) Receiver at 40Ghz. Architecture with blocks looks like:
There is also a bandpass filter in front of the LNA. (todo: make a nice block diagram)
Furthermore, it is assumed that at 40GHz, the same regulations are in place as for 60GHz with regards to the EIRP, and th 2GHz of bandwidth is available. Thus we arrive at a received power of -57dBm:
Our link budget aiming at a Gain of 40 dB to increase the signal to -17dBM
For the oscillator design we went for a PMOS cross coupled oscillator. Using a LC tank the desired frequency of 40GHz is achieved. And a inverter buffer stage to isolate the device.
using the following values:
The control voltage is able to tune the the oscillating frequency from 36 to 44 so a syntysiser is able to tune to the correct frequency.
Here the tuning range due to the variable capacitors can be seen. By changing the voltage from 500mV to 1V the desired frequency can be choosen ranging from 36GHz (1V) to 44Ghz(500mV). Resulting in a tuning range of -+10%.
The oscillator uses L = 400 p and a variable capacitor as tank.
Frequency = 44.7 GHz V_control = 0.5V displaying Vout_plus and Vout_minus
Frequency = 36.1 GHz V_control = 1V displaying Vout_plus and Vout_minus
The mixer is a dual-balanced mixer with a common-source amplifier output stage with parameters:
When feeded with an 40GHz OOK signal with a OOK period of 1ns (1GHz), the output as compared to the input 'bits' is as follows:
It can be seen that at the mixer output, transmitted bits can be clearly distinguished.
The mixer uses 225.4uW of power, or 0.226pJ per bit.
The LNA was designed by UMS ph10 technology. RLC feedback in the third cascade has been used simultaneously in order to achieve improved stability over the whole frequency range and gain to got flatness in gain characteristic for the working frequency band. The LNA has the following parameters:
Freq. band: 39 - 41 GHz
Gain: 20.5 ... 21 dB
Noise: 1.5 ... 1.6 dB
S11: -10 dB
S22: -15 dB
Vdd: 6 V
Idd: 14 mA
IP3: -17 dBm (bad result, I want to improve it in the future )
The frequency divider for the synthesizer is created with dynamic logic and can be seen below:
The input and output can be seen in the plot below:
The maximum power dissipation is around 100uW, with an average of around 50uW, which is around 0.1pJ/bit maximum.