There is chosen to design an OOK transmitter because of the simplicity and the low power consumption. Instead of using a "traditional" architecture where a seperate mixer and PA are used, there is chosen to combine the 2. By switching the PA, the OOK modulation is generated. 

Image  Source: “60-GHz Gigabits-Per-Second OOK Modulator With High Output Power in 90-nm CMOS”


The oscillator design is based on a Pushpush LC VCO design. Below is a schematic layout view of the oscillator. The advantage of using this desing over a NMOS only design is that here, the current is basically pushed out of the supply

 Push-Push LC VCO

The advantage of using this desing over the NMOS only design shown below, is that the pushpush LC oscillator is able to push current out of the V+ and V- ports. 



Working principle

The RLC tank in the center of the design oscillates at the set frequency, however, as it is as it is lossy, the oscillation will quickly fade. The NMOS transistors at the bottom of the design (Q7 and Bias) are designed as a current mirror, keeping the transistors in saturation.

Choosing the RLC tank to have a high Q-factor means making the inductor as large as possible. The oscillating frequency is determined by the LC combination, and the resistor value also affects the Q-factor positively, but also introduces more thermal noise.  On the other hand, a larger L will also reduce the gain. 


In the diagram, the working principle is explained in a very rudimentary way. The RLC tank causes the transistors to basically switch from state 1 and back. The red arrow indicates the current flow. Of course, the transistors never fully switch off and on, but it simplifies the explanation. 

The basic layout of the oscillator is based on a LC VCO with NMOS current source. Using the push-pull effect of PMOS transistors at the supply, and NMOS transistors at the ground side, the 1/f noise decreases as the output signal is more isolated from substrate and supply noise, compared to just NMOS or PMOS transistor pairs. Next to that, this design is able to supply more current as well, which is needed to drive the frequency doubler, as it 'pushes' the supply either high or low. The frequency is steered by a RLC tank circuit. Choosing as high as possible inductor gives a higher Q factor. The resistor ... 


transistor sizes

The transistors are all of W = 2u and L = 50n, with a multiplier of 5. The multiplier causes the transistors to be effectively 10u broad. The width is needed to pass the bias current of 1mA.

output limiting diodes

At the V+ and V- terminals, after the capacitor used for AC-coupling, output limiting diodes are placed (NMOS transistor with drain and gate connected (V_gs = V_ds)) such that the oscillator does not break itself. The effect is minimally noticable in this design, as the match between the oscillator and frequency doubler is quite okay and the oscillation is not rail-to-rail. 


Different methods of tuning are possible. Introducint PVT in the design will show that the oscillating frequency is not always what it was designed for. 



Either using different values capacitors in an array, and a switch (dis)connecting them, or by using a varactor. The varactor is a MOS transistor with drain and source connected to one side, and the gate connected to the other side. Connecting them in the following configuration in the circuit gives the ability to change the capacitance as a function of voltage C(V). This in turn is able to control the oscillating frequency. 

Digitally Controlled Oscillator (DCO)

A DCO can be implemented using a bank of different size capacitors and a controller to enable or disable them, based on the output frequency. Additional capacitors can be sized binary unary or any other combination, which will affect the tuning range and/or precision.

Bias current

Adjusting the bias current provided by the current supply also introduces ability to tune the circuit 


Output signal


From simulations, the output frequency of the oscillator depends of course on the load. Connected in the system, the oscillator is connected differentially to a frequency doubler, giving output of 1Vpp centered around 0V. The amplitude is not exactly symmetric, but very close, to 0.05V. Next to that, there are no significant undesired oscillations on the output either.



The peak shown in the spectrum plot is at 32.6GHz at -6.8dB, all sidelobes in the spectrum up to 100G are surpressed to at least -28dB. The frequency should be retuned to 30GHz using the tuning methods described above, switching in additional capacitors or supplying voltage to varactors will bring the frequency down to 30GHz. The power consumption is equal to 1pJ/bit


Frequency Doubler

The frequency doubler is made out of the following circuit:


By applying two sinusoids with 180 degr. phase shift to the gates of M3 and M4, we will have an output with double the frequency as the input. Both transistors operate in saturation, so that the non-linear operation can produce a doubled frequency.

Lets start analyzing the doubler by first looking at the basic circuit. By removing all inductors and capacitors present, we are left over with:


If we now apply the sinusoids at the input we get:


Where the upper two plots are the drain currents of both transistors and the lower plot is the gate voltage of M3 corresponding to the upper current. Now V_g is fixed at 1V. However for the transistors to be able to double the frequency the drain voltages should be able to fluctuate.

Therefor we add an inductor between V_drain and V_DD. Now we get the following:



Where the upper two plots are again the drain currents, there-after the gate voltage of M3, and the output voltage at the drain.


Data interface

The data interface consist of three inverter stages after the data input(generated in cadence). The optimum ratio between the normalized delay and the number of stages is around 3.5. Since each inverter stage introduces more area and power it was chosen to choose 3 stages for both transistors used in the PA. The Cload was already determined by the PA and was thus fixed, it was chosen due to optimization with the coil for 60GHz. The higher Cload increases the power dissipation in two ways W/L needs to be higher and Ceff becomes bigger. In order to reduce the power consumption the following steps were taken during the design:

Vth was chosen as high as possible, to have a lower leakage current during the static power consumption(VTH). But after some testing at 2GS/s it was determent that leakage was not the dominant power consumption component in the data interface block. After some power dissipation comparison between VTH and VTL it was determined that VTL transistors is the prefered way to go. The end result difference is VTH= 1.05pJ/bit and VTL = 0.91fJ/bit. This behavior can be explained as follow: The VTL can switch faster with the same W/L, this makes it possible to use transistor with smaller W/L -> reducing the parasitic capicitance and thus making the dynamic power lower.


The next step is to minimize Vdd, since the behaviour of Vdd is quadratic related to the power consumption. For correct behaviour, without blowing up the transistor Vdd is set at 900mV (anothe reason for 900mV is to create comminality of voltage sources). An offset is introduced to Vss to not go below 0V. Therefore Vss is set to 0.1mV. The data input can be lower, since the inverter will pull up the data towards the rails, thus the data was chosen for 0.3mV to 0.7mV with an introduced rise and fall time of 100fs, since an infinite slope is not possible (some free gain due to the digital behavior, nice).

The multiplier stage was set to 1,2,4 after some testing. The optimal ratio between Wp and Wn was found to be around Wp = 1.9Wn for freePDK45 to get the best rise/fall time. This ratio will thus be maintained especially in the first inverter, since this is the dominant one for the rise/fall time. The last stage needs the largest W in order to fill the capacitance in time (RC time).

Results are shown below:


The circuitry used for the Data Interface.


Each step of the Data Interface block.

Pdyn = Fs * Cload*Vdd^2

Psc = tsc*Vdd*Ipeak*f (minimized by keeping the rise times equal and steep)

Pstatic = Istatic*Vdd (higher due to VTL transistors)


Power amplifier

The chosen PA is a two-stage CS amplifier based on a current reuse technique. The PA will be switched by the data interface which changes the gate bias of the NMOS devices. 60GHz signal passes through interstage matching circuit (L3, C1, L5). L2 blocks the 60GHz signal.

The signal of the data interface is applied at the Data1 and Data2 net. The 60GHz signal will be supplied at the VCO net. The advantage of this PA structure is that it ideally only consumes power when the input data is 1. The circuit with the used values is given below.


These values give the following output.


This is a 0.93Vpp signal, which translates to a 3.34dBm output. 

In the following graph the S parameters of the PA can be seen. This is when the data signal is 1.


The power gain is +9.4dB and the 1dB compression point is at -762mdBm. See graph below.


System overview


For a data signal at 2 GHz, the components use the following power:

OscillatorDoublerInverter + Power AmplifierTotal



Output plots towards antenna load (50 ohms)

This uses all sources at 1V, differentiating them between 0.9 and 1.1V changes the power usage and output slightly. The oscillator, doubler and power amplifier power usage goes down as the modulation frequency increases. Only the power usage of the inverter heavily depends on the modulation frequency, and thus determined the limit here.

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