This is where you can put anything you want to share. You can also create additional pages and link to these pages from this one by creating a link to a non-existing page. When you click on this link, you will be asked whether you want to create a new page.
You could e.g. add pages for each student individually to present the results of your assignment and/or pages for individual subcircuits where you collect information about these subcircuits etc. It's completely up to you!
For now I've included the picture of the system options & the blackboard as well as the blackboard pictures & spreadsheet from the 3rd lecture.
- Student Contributions page for PA missing so included here for the time being ******
Gain = 10dB
Noise Factor = 40dB
IP3 = 10dB
Input type: Differential
Output type: Differential matched to 50 Ohm
First an architecture was decided upon. This architecture can be seen below:
The differential pair reduces the effect of supply or ground voltage noise.
A thing to worry about is mismatch between transistor M2 and M3 will cause an imbalance in current, and a offset in the ouput voltage.
A problem we encountered was the gain that the CD4007 MOSFETs can provide. Below a picture is shown of the sweep of the bias voltage of the PMOS versus the current that the MOSFET produces via its transconductance.
From this picture the Gm(max) can be determined to be ~32uA/V.
With a 50 Ohm output impedance of the differential amplifier this results in a maximum gain of 1.6V/V.
This is only achievable for a high Vsd over the PMOS transistor, since channel length modulation increases the current.
In the differential amplifier however, a cascode of a current source together with the differential PMOS transistors is present.
This further reduces the gain of the transistor, making the gain of 10dB not achievable as of this moment in our simulations.
The maximum output voltage swing that is achieved is observed as ~40uVpp.
- END OF PA SECTION *****
- Synthesizer Section *****
- End of Synthesizer Section *****